The present invention relates to a technology effective when applied to a damascene wiring technology in a manufacturing method of a semiconductor integrated circuit device (or a semiconductor device).
Japanese Unexamined Patent Publication No. 2004-14868 discloses a technology of, in removal of electrostatic charge (static elimination) from a wafer after plasma etching treatment performed in the same chamber of a plasma treatment apparatus, carrying out the removal by using argon plasma thorough a circumferential edge of a wafer stage configuring an electrostatic chuck while using the wafer stage as a high-resistance conductor.
Japanese Unexamined Patent Publication No. 2007-258636 discloses a technology of, in removal of electrostatic charge from a wafer after plasma etching treatment performed in the same chamber of a plasma treatment apparatus, carrying out the removal by using argon plasma while floating one end of the wafer on a wafer stage configuring an electrostatic chuck.